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Generating hardware assertion checkers : For hardware verification, emulation, post-fabrication debugging and on-line monitoring
This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.
Creating Assertion-Based Verification IP
The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.
Constraint-Based Verification
Constraint-Based Verifcation covers the emerging field in functional verification of electronic designs thats is now commonly referred to by this name. Topics are developed in the context of a wide range of dynamic and static verification approaches including stimulation, emulation and formal methods. The goal is to show how constraints, or assertions, can be used toward automating the generation of testbenches, resulting in a seamless verifcation flow. Topics such as verification coverage, and connection with assertion-based verification are also covered.
A Practical Introduction to PSL
Practical Introduction to PSL is primarily targeted to hardware designers and verification engineers who plan to use PSL. This book is also of interest to students of temporal logic. The formal semantics of PSL are included as an appendix, and bibliographical notes include pointers to some of the main theoretical works.
