الصفحة 1
الصفحة 1
Integrated circuit and system design : Power and timing modeling, optimization and simulation ; 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
Papers cover high level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, and more.
Closing the POWER gap between ASIC & custom : Tools and techniques for low power design
Details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology.Important topics include: - Microarchitectural techniques to reduce energy per operation / - Power reduction with timing slack from pipelining / - Analysis of the benefits of using multiple supply and threshold voltages / - Placement techniques for multiple supply voltages - Verification for multiple voltage domains / - Improved algorithms for gate sizing, and assignment of supply and threshold voltages / - Power gating design automation to reduce leakage / - Relationships among statistical timing, power analysis, and parametric yield optimization / Design examples illustrate that these techniques can improve energy efficiency by two to three times.
