الصفحة 1
الصفحة 1
Integration and innovation orient to e-society ; Vol.2 ; 7th IFIP International Conference on e-business, e-Services, and e-Society (I3E2007), October 10-12, Wuhan, China
The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing.
Low-Power High-Speed ADCs for Nanometer CMOS Integration
Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested.
