الصفحة 1
الصفحة 1
Wireless Transceiver Systems Design
This book illustrates true cross-disciplinary electronic system-level design with examples in algorithm-architecture co-design, mixed-signal algorithm and architecture co-design, and cross-layer system exploration. It also focuses on three recurring themes, the preference for scalable and reusable architectual concepts, proof-of-concept through actual design and experimental verification, and consequent analysis of design steps and their development into a methodology.Wireless Transceiver Systems Design is a valuable reference for specialists in the field of OFDM transceiver design.
Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms
In Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, such originally independent approaches are combined in order to enable the development of highly optimized programmable platforms.The first chapters of this book summarize the state of the art in all three involved fields separately: general system level design, communication modeling, and processor modeling. The main chapters then present a methodology and the associated tooling for enabling design space exploration as well as a successive refinement flow for the design of optimized MP-SoCs with a high degree of automation.
Functional Verification of Programmable Embedded Architectures : A Top-Down Approach
This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric.
CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications
Focuses on optical communications for short and very short distance applications and discusses the monolithic integration of optical receivers with processing elements in standard CMOS technologies. CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications provides the reader with the necessary background knowledge to fully understand the trade-offs in short-distance communication receiver design and presents the key issues to be addressed in the development of such receivers in CMOS technologies. Moreover, novel design approaches are presented. A system-level design methodology allows for the impact analysis of different block specifications and system-wide design optimization. Statistical models are used for design space exploration in the scope of jitter tolerance analysis of clock recovery circuits.
