Low-Power High-Speed ADCs for Nanometer CMOS Integration

Low-Power High-Speed ADCs for Nanometer CMOS Integration

المؤلف
Zhiheng Cao, Shouli Yan
سنة النشر
2008
الناشر
Springer
لغة الملف
انكليزي
نوع الملف
Book
تصنيف الكتاب
Engineering

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested.


الكلمات المفتاحية: Engineering / Analog-to-digital converters / CMOS / Clock-multipliers / Deep-submicron CMOS / Filter / Multiplexer / Nanometer CMOS / Phase-lock loop