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Interconnect Noise Optimization in Nanometer Technologies
The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
Full-Chip Nanometer Routing Techniques
From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability
Electromagnetic Compatibility of Integrated Circuits : Techniques for low emission and susceptibility
Electromagnetic Compatibility of Integrated Circuits: Techniques for Low Emission and Susceptibility focuses on the electromagnetic compatibility of integrated circuits. The basic concepts, theory, and an extensive historical review of integrated circuit emission and susceptibility are provided. Standardized measurement methods are detailed through various case studies. EMC models for the core, I/Os, supply network, and packaging are described with applications to conducted switching noise, signal integrity, near-field and radiated noise. Case studies from different companies and research laboratories are presented with in-depth descriptions of the ICs, test set-ups, and comparisons between measurements and simulations. Specific guidelines for achieving low emission and susceptibility derived from the experience of EMC experts are presented.
Digital Timing Measurements : From Scopes and Probes to Timing and Jitter
As many circuits and applications now enter the Gigahertz frequency range, accurate digital timing measurements have become crucial in the design, verification, characterization, and application of electronic circuits. To be successful in this endeavour, an engineer needs a knowledge base covering instrumentation, measurement techniques, signal integrity, jitter and timing concepts, and statistics. Very often even the most experienced digital test engineers, while mastering some of those subjects, lack systematic knowledge or experience in the high speed signal area.
