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ESD Protection Device and Circuit Design for Advanced CMOS Technologies
ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains.
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies : Process-Aware SRAM Design and Test
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing.
