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Hardware and software, verification and testing ; 2nd International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006, Revised Selected Papers
The Haifa Verification Conference 2006 took place for the second year in a row at the IBM Haifa Research Lab and at the Haifa University in Israel during October 23–26, 2006. The verification conference was a three-day, single-track conference followed by a one-day tutorial on PSL.
Functional Verification of Programmable Embedded Architectures : A Top-Down Approach
This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric.
Functional verification coverage measurement and analysis
Functional Verification Coverage Measurement and Analysis addresses a means of quantitatively assessing functional verification progress. Without this process, design and verification engineers, and their management, are left guessing whether or not they have completed verifying the device they are designing. Using the techniques described in this book, they will learn how to build a toolset which allows them to know how close they are to functional closure.
Effective Functional Verification : Principles and Processes
Effective Functional Verification is organized into 4 parts. The first part contains 3 chapters designed appeal to newcomers and experienced people to the field. There is a survey of various verification methodologies and a discussion of them. The second part with 3 chapters is targeted towards people in management and higher up on the experience ladders. New verification engineers reading these chapters learn what is expected and how things work in verification. Some case studies are also presented with analysis of proposed improvements. The last two parts are the result of experience of several years. It goes into how to optimize a verification plan and an environment and how to get results effectively.
Constraint-Based Verification
Constraint-Based Verifcation covers the emerging field in functional verification of electronic designs thats is now commonly referred to by this name. Topics are developed in the context of a wide range of dynamic and static verification approaches including stimulation, emulation and formal methods. The goal is to show how constraints, or assertions, can be used toward automating the generation of testbenches, resulting in a seamless verifcation flow. Topics such as verification coverage, and connection with assertion-based verification are also covered.
