Interconnect Noise Optimization in Nanometer Technologies
Publication year: 2006
ISBN: 978-0-387-29366-0
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The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
Subject: Engineering, 3D, CAD, algorithms, complexity, computer-aided design (CAD), integrated circuit, layout, metal-oxide-semiconductor transistor, optimization, simulation
