High Performance Embedded Architectures and Compilers
Publication year: 2005
ISBN: 978-3-540-32272-6
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The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.
Subject: Computer Science, Compiler, compiler techniques, computer architecture, dynamic compilation, embedded systems, high-performance architecture, memory system organization, network computing, network processors, parallel architectures, performance evaluation, processor architectures, reconfigurable architectures, secured computing, security processors
