Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Publication year: 2007
ISBN: 978-1-4020-5897-4
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this book explores a collaborative approach by proposing novel memory hierarchies and software optimization techniques for the optimal utilization of these memory hierarchies. Linking memory architecture design with memory-architecture aware compilation results in fast, energy-efficient and timing predictable memory accesses.The evaluation of the optimization techniques using real-life benchmarks for a single processor system, a multiprocessor system-on-chip (SoC) and for a digital signal processor system, reports significant reductions in the energy consumption and performance improvement of these systems. The book presents a wide range of optimizations, progressively increasing in the complexity of analysis and of memory hierarchies. The final chapter covers optimization techniques for applications consisting of multiple processes found in most modern embedded devices.
Subject: Engineering, architecture, compiler optimizations, complexity, digital signal processor, embedded systems, energy, power optimizations, memory architectures, optimization, processor, system design, system on chip (SoC), timing predictability
