Digital Phase Lock Loops
Publication year: 2007
ISBN: 978-0-387-32864-5
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This exciting new book covers various types of digital phase lock loops. It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition. These requirements are of paramount importance in many applications including wireless communications, consumer electronics and others. Digital Phase Lock Loops then illustrates the process of converting the TDTL class of digital phase lock loops for implementation on an FPGA-based reconfigurable system. These devices are being utilized in software-defined radio, DSP-based designs and many other communication and electronic systems to implement complex high-speed algorithms.
Subject: Engineering, Digital phase lock loops, Digital phase lock loops applications, Digital phase lock loops noise analysis, FPGA, FPGA-based Reconfigurable Systems, Filter, Frequency estimation, Hilbert Transforms, Switch, Time Delay Digital Tanlock Loops, communication, complexity, development, digital signal processor, system analysis
