Wafer Level 3-D ICs Process Technology
Publication year: 2008
ISBN: 978-0-387-76534-1
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The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration.
Subject: Engineering, Applications enabled by 3-D integration, CMOS, Diffusion, Technologie, Three-dimensional (3-D) integration, Through Silicon vias (TSVs), Wafer, Wafer bonding, Wafer-Level 3-D Technology Platforms, circuit, design, integrated circuit, silicon, technology, three dimensional integrated circuit
