System Verilog for Verification : A Guide to Learning the Testbench Language Features
Publication year: 2008
ISBN: 978-0-387-76530-3
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This expanded book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. It contains a new chapter covering programs and interfaces as well as chapters with updated information.
Subject: Engineering / Hardware / SystemVerilog / Verilog / field-effect transistor / integrated circuit / simulation / static-induction transistor / statistics / verification / Circuits and Systems / Electronics and Microelectronics / Instrumentation / Computer-Aided Engineering (CAD, CAE) and Design / Computer Hardware / Electrical Engineering
