Creating Assertion-Based Verification IP
Publication year: 2008
ISBN: 978-0-387-68398-0
Internet Resource: Please Login to download book
The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.
Subject: Engineering, Assertion-Based, Foster, Krolnik, SystemVerilog, Verification, Verilog, integrated circuits, optimization, simulation
