Low-Power High-Speed ADCs for Nanometer CMOS Integration
Publication year: 2008
ISBN: 978-1-4020-8450-8
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Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested.
Subject: Engineering, Analog-to-digital converters, CMOS, Clock-multipliers, Deep-submicron CMOS, Filter, Multiplexer, Nanometer CMOS, Phase-lock loop
