Hardware Verification with SystemVerilog
Publication year: 2007
ISBN: 978-0-387-71740-1
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Verification is increasingly complex, and SystemVerilog is one of the languages that the verification community is turning to. However, no language by itself can guarantee success without proper techniques. Object-oriented programming (OOP), with its focus on managing complexity, is ideally suited to this task. With this handbook—the first to focus on applying OOP to SystemVerilog—we’ll show how to manage complexity by using layers of abstraction and base classes. By adapting these techniques, you will write more "reasonable" code, and build efficient and reusable verification components. Both a learning tool and a reference, this handbook contains hundreds of real-world code snippets and three professional verification-system examples.
Subject: Engineering, C++ programming language, Factor, Hardware, Interface, Open-Source, SystemVerilog, Verilog, complexity, computer-aided design (CAD), construction, hardware verification, layers, programming, testing, verification
