SystemVerilog for Verification
Publication year: 2006
: 978-0-387-27038-8
Provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. This book explains methodology concepts for constructing testbenches that are modular and reusable.
: Engineering, Hardware, Interface, Software, Spear, SystemVerilog, Verilog, communication, design, methodology concepts, programming, testbenches, testing, verification
