SystemVerilog for Design
Publication year: 2006
: 978-0-387-36495-7
SystemVerilog is a rich set of extensions to the Verilog Hardware Description Language (Verilog HDL). SystemVerilog for Design describes the correct usage of these extensions for modeling digital designs.
: Engineering, Design Guide, Hardware, Hardwarebeschreibungssprache, Interface, Standard, Sutherland, SystemVerilog, Verilog, computer-aided design (CAD), modeling, simulation
