Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Publication year: 2006
: 978-1-4020-4826-5
Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.
: Engineering, Augmented Reality, Electronic System Level (ESL), Multi-Processor System-on-Chip (MP-SoC), Network-on-Chip (NoC), Performance, Processing, QoS, Simulation, SystemC, Transaction Level Modeling (TLM), architecture, model, modeling, organization, system on chip (SoC)
