Symbolic Analysis and Reduction of VLSI Circuits
Publication year: 2005
: 978-0-387-23905-7
Efficient modeling and reduction of both the passive and active circuits is essential for hierarchical and IP-based reuse design paradigms. Symbolic Analysis and Reducation of VLSI Circuits presents the symbolic approach to the modeling and reduction of both the passive parasitic linear networks and active analog circuits. It reviews classic symbolic analysis methods and presents state-of-art developments for interconnect reduction and the behavioral modeling of active analog circuits. The text includes the most updated discoveries such as Y-Delta transformation and DDD-graph symbolic representation which allow analysis and modeling of much larger circuitry than ever before.
: Engineering, VLSI, Analog, Analog Circuit Analysis, analog circuit design, analog design, Integrated Circuit, linear circuit reduction, Mtopological circuit analysis
