Clock Generators for SOC Processors
Publication year: 2005
: 978-1-4020-8080-7
On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior.
: Engineering, CMOS, Fahim, Filter, digital signal processor, drift transistor, published, system on chip (SoC)
