الصفحة 1
الصفحة 1
Modeling and Simulation for RF System Design
The focus of Modeling and Simulation for RF System Design lies on RF specific modeling and simulation methods and the consideration of system and circuit level descriptions. It contains application-oriented training material for RF designers which combines the presentation of a mixed-signal design flow.
Hardware Verification with SystemVerilog : An Object-Oriented Framework
Verification is increasingly complex, and SystemVerilog is one of the languages that the verification community is turning to. However, no language by itself can guarantee success without proper techniques. Object-oriented programming (OOP), with its focus on managing complexity, is ideally suited to this task. With this handbook—the first to focus on applying OOP to SystemVerilog—we’ll show how to manage complexity by using layers of abstraction and base classes. By adapting these techniques, you will write more "reasonable" code, and build efficient and reusable verification components. Both a learning tool and a reference, this handbook contains hundreds of real-world code snippets and three professional verification-system examples.
Hardware Verification with C++ : A Practitioner’s Handbook
Part I makes the case for C++, and shows a standard verification system using object-oriented programming (OOP). Part II presents two open-source C++ libraries that enable efficient verification with C++ -- Teal, a C++ to Verilog interface, and Truss, a standard verification framework. Part III focuses on OOP with examples from real verification projects. Part IV puts it all together showing complete block-level and system-level verification systems. "The handbook provides a clear understanding of object-oriented programming, and how it applies to hardware verification. It is clear to me that C++, together with Teal and Truss, could form a strong platform for the next generation of hardware verification."
Digital VLSI Systems Design : A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog
The book presents new material and theory as well as synthesis of recent work with complete Project Designs using industry standard CAD tools and FPGA boards, enabling the serious readers to design VLSI Systems on their own. The reader is taken step by step through the design right from implementing a single digital gate to a massive design consuming well over 100,000 gates. The Verilog codes developed for these designs are universal and can work on any FPGA or ASIC and are technology independent. The book presents the development of novel algorithms and architectures for optimum realization of high tech. products. All the design codes developed in this book are Register Transfer Level (RTL) compliant and can be readily used or amended to suit new projects.
Digital VLSI Design with Verilog : A Textbook from Silicon Valley Technical Institute
Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.
Digital Signal Processing with Field Programmable Gate Arrays
Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing as novel FPGA families are replacing ASICs and PDSPs for front-end digital signal processing algorithms. So the efficient implementation of these algorithms is critical and is the main goal of this book. It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems. A case study in the first chapter is the basis for more than 40 design examples throughout. The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, advanced algorithms with high future potential, and adaptive filters. Each chapter contains exercises. The VERILOG source code and a glossary are given in the appendices. This edition has a new chapter on microprocessors, new sections on special functions using MAC calls, intellectual property core design and arbitrary sampling rate converters, and over 100 new exercises.
Creating Assertion-Based Verification IP
The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.
CPU Design : Answers to Frequently Asked Questions
Chandra’s book provides a practical overview of Microprocessor and high end ASIC design as practiced today. It is a valuable addition to the literature on CPU design, and is made possible by Chandra’s unique combination of extensive hands-on CPU design experience at companies such as AMD and Sun Microsystems and a passion for writing
Constraint-Based Verification
Constraint-Based Verifcation covers the emerging field in functional verification of electronic designs thats is now commonly referred to by this name. Topics are developed in the context of a wide range of dynamic and static verification approaches including stimulation, emulation and formal methods. The goal is to show how constraints, or assertions, can be used toward automating the generation of testbenches, resulting in a seamless verifcation flow. Topics such as verification coverage, and connection with assertion-based verification are also covered.
Assertion-Based Design
Chapter 3 Specifying RTL Properties 61 3. 3 Declarative versus procedural 67 3. 3 RTL assertion specification techniques 68 RTL invariant assertions 69 3. 2 Declaring properties with PSL 72 RTL cycle related assertions 73 3. 3 3. 1 Immediate assertions 84 3. 3 System functions 95 3. 3 Assertions across simulation time slots 111 4.
A Practical Guide for SystemVerilog Assertions
SystemVerilog language consists of three very specific areas of constructs - design, assertions and testbench. This guide shows how to use the language to solve real verification problems. It examines how to verify complex protocols and memories using SVA with seeral examples.
