الصفحة 1
الصفحة 1
CMOS single chip fast frequency hopping synthesizers for Wireless multi-gigahertz applications : Design methodology, analysis, and implementation
Describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones. The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-mode fractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details.
Low Power VCO Design in CMOS
The performance of voltage controlled oscillators (VCO) is of extreme importance for any telecommunication or data communication system. This practical guide develops a systematic, fully-integrated LC-VCO design for low power and low phase noise, especially useful to meet the demands on mobile devices such as cell phones. The proposed VCO design approaches are experimentally verified with several fully integrated CMOS VCOs. The concise presentation is offered in three parts (VCO design; CMOS devices for VCO design; and fully-integrated CMOS DESIGNS) and supplemented by an appendix summarizing the state of the art.
