الصفحة 1
الصفحة 1
New Horizons of Parallel and Distributed Computing
Parallel and distributed computing is one of the foremost technologies for shaping future research and development activities in academia and industry. Hyperthreading in Intel processors, hypertransport links in next generation AMD processors, multicore silicon in today’s high-end microprocessors, emerging cluster and grid computing, has moved parallel/distributed computing into the mainstream of computing. New Horizons of Parallel and Distributed Computing is a collection of self-contained chapters written by pioneers and researchers to provide solutions for newly emerging problems in this field. This volume will not only provide novel ideas, work in progress and state-of-the-art techniques in the field, but also stimulate future research activities in the area of parallel and distributed computing with applications. New Horizons of Parallel and Distributed Computing is intended for researchers and graduate students in computer science and electrical engineering, as well as researchers and developers in industry. This book can be used as a textbook and a reference for use by students, researchers, and developers.
Microprocessor 5 : Software and hardware aspects of development, debugging and testing - the microcomputer
Focuses more particularly on the first two generations of microprocessors, those that handle 4- and 8- bit integers. Microprocessor 5 – the fifth and final volume of this series of books – first presents the hardware and software aspects of the development chain of a microprocessor-based digital system. Finally, to round up the series and offer a historical perspective, the architectures of the first microcomputers are detailed. A comprehensive approach is used, with examples drawn from current and past technologies that illustrate theoretical concepts, making them accessible.
Microprocessor 2 : Communication in a digital system
Focuses more particularly on the first generations of microprocessors, that is to say those that handle integers in 4 and 8-bit formats. The first chapter presents the calculation function and reminds the memory function. The following is devoted to notions of calculation model and architecture. The concept of bus is then presented. Chapters 4 and 5 can then address the internal organization and operation of the microprocessor first in hardware and then software. The mechanism of the function call, conventional and interrupted, is more particularly detailed in a separate chapter. The book ends with a presentation of architectures of the first microcomputers for a historical perspective. The knowledge is presented in the most exhaustive way possible with examples drawn from current and old technologies that illustrate and make accessible the theoretical concepts. Each chapter ends if necessary with corrected exercises and a bibliography. The list of acronyms used and an index are at the end of the book.
High performance computing - HiPC 2004 ; 11th International Conference, Bangalore, India, December 19-22, 2004, Proceedings
Keynote Addresses.- Rethinking Computer Architecture Research.- Event Servers for Crisis Management.- DIET: Building Problem Solving Environments for the Grid.- The Future Evolution of High-Performance Microprocessors.- Low Power Robust Computing.- Networks and Games.- Plenary Session - Best Papers.- An Incentive Driven Lookup Protocol for Chord-Based Peer-to-Peer (P2P) Networks.- A Novel Battery Aware MAC Protocol for Ad Hoc Wireless Networks, and other
Electronic Devices and Circuit Design : Challenges and Applications in the Internet of Things
Offers a broad view of the challenges of electronic devices and circuits for IoT applications. The book presents the basic concepts and fundamentals behind new low power, high-speed efficient devices, circuits, and systems in addition to CMOS. It provides an understanding of new materials to improve device performance with smaller dimensions and lower costs. It also looks at the new methodologies to enhance system performance and provides key parameters for exploring the devices and circuit performance based on smart applications.
Digital Signal Processing with Field Programmable Gate Arrays
Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing as novel FPGA families are replacing ASICs and PDSPs for front-end digital signal processing algorithms. So the efficient implementation of these algorithms is critical and is the main goal of this book. It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems. A case study in the first chapter is the basis for more than 40 design examples throughout. The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, advanced algorithms with high future potential, and adaptive filters. Each chapter contains exercises. The VERILOG source code and a glossary are given in the appendices. This edition has a new chapter on microprocessors, new sections on special functions using MAC calls, intellectual property core design and arbitrary sampling rate converters, and over 100 new exercises.
Design of Systems on a Chip : Design and Test
Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip.
