الصفحة 1
الصفحة 1
New Methods of Concurrent Checking
New Methods of Concurrent Checking is the ultimate reference to answer the question as to how the best possible state-of-the-art error detection circuits can be designed. The most effective methods of concurrent checking for digital circuits are comprehensively described which were developed in the last 15 years. Some of the methods are published for the first time. How concurrent checking can be combined with soft error correction is also shown for the first time. This book is invaluable in considering the design of reliable systems in the emerging Nanotechnologies with an associated growing number of transient faults.
Nanoscale Transistors : Device Physics, Modeling and Simulation
The book is a useful reference for senior-level or graduate-level courses on nanoelectronics, modeling and simulation. Chapter 1 reviews some basic concepts, and Chapter 2 summarizes the essentials of traditional semiconductor devices, digital circuits, and systems. This material provides a baseline against which new devices can be assessed. Chapters 3 and 4 present a non-traditional view of the MOSFET using concepts that are valid at nanoscale. Chapter 5 applies the same concepts to nanotube FET as an example of how to extend the concepts to revolutionary nanotransistors. Chapter 6 explores the limits of devices by discussing conduction in single molecules.
Model and Design of Improved Current Mode Logic Gates : Differential and Single-ended
This book presents MOSFET-based current mode logic (CML) topologies, which increase the speed, and lower the transistor count, supply voltage and power consumption. The improved topologies modify the conventional PDN, load, and the current source sections of the basic CML gates.
Model and Design of Bipolar and MOS Current-Mode Logic : CML, ECL and SCL Digital Circuits
many works and results have been published which reinforce the importance of Current-Mode digital circuits. In the topic of Current-Mode digital circuits, the authors properly exploited classical paradigms developed and used in the analog circuit domain (a topic in which one of the authors maturated a great experience).
Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications
Fully-depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V. The topics include the minimum required knowledge of the fabrication of SOI substrates; FD-SOI devices and the latest developments in device and process technologies; and ultralow-voltage circuits, such as digital circuits, analog/RF circuits, and DC-DC converters. Each ultra-low-power technique related to devices and circuits is fully explained using figures to help understanding.
Evolvable systems : From biology to hardware ; 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings
This book constitutes the refereed proceedings of the 8th International Conference on Evolvable Systems, ICES 2008, held in Prague, Czech Republic, in September 2008.The 28 revised full papers and 14 revised poster papers presented were carefully reviewed and selected from 52 submissions. The papers are organized in topical sections on evolution of analog circuits, evolution of digital circuits, hardware-software codesign and platforms for adaptive systems, evolutionary robotics, development, real-world applications, evolutionary networking, evolvable artificial neural networks, and transistor-level circuit evolution.
Digital fundamentals
For courses in digital circuits, digital systems (including design and analysis), digital fundamentals, digital logic, and introduction to computers Digital Fundamentals, Eleventh Edition, continues its long and respected tradition of offering students a strong foundation in the core fundamentals of digital technology, providing basic concepts reinforced by plentiful illustrations, examples, exercises, and applications.
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits.
